Semi Doped

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GlobalFoundries Thomas Barber: CPO, Silicon Photonics, 300mm, SiGe, OCI, NRZ Aug 07, 2026

Show notes

The physical limits of copper are forcing a shift to optical interconnects in AI data centers. Austin sits down with GlobalFoundries' Thomas Barber to unpack why GF thinks it can lead that transition twice over: once with its long-running silicon photonics platform, and again with the specialty Silicon Germanium process the industry needs to drive it.

"The enemy to me right now is copper. I'm trying to beat copper, right? If TSMC wins and we win, that's great because we're both displacing copper. And until all the copper is gone, there's plenty of market to go around."
— Thomas Barber, GlobalFoundries

Key Takeaways:
- Copper's usable range halves every time the data rate doubles, and 200 Gbps/lane inside a rack-scale AI cluster is already past the point copper can handle.

- CPO's real win isn't speed, it's power: saving 20-25 pJ/bit frees part of a data center's fixed 50-100 MW budget to go toward compute instead of moving bits.

- GlobalFoundries leads photonics revenue for an unglamorous reason: it moved to 300mm wafers early, which yields 2.25x more die per wafer than the 200mm lines rivals still run.

- CPO can end up more reliable than the pluggables it's replacing, not less, because it deletes the physical plug connector, and dust at that connector is the leading cause of field failures.

- The OCI MSA picks NRZ over faster PAM4, deliberately going wide and slow, because NRZ's native bit error rate is a million times lower, which simplifies the receiver and cuts power.

- GlobalFoundries stacks two specialty processes into one edge: micro-mirror couplers on the photonic side, and Silicon Germanium transistors hitting 350-400 GHz on the electrical side driving them.

- The real competitor for silicon photonics isn't another foundry, it's copper itself — and that market is big enough that GlobalFoundries and TSMC can both win without taking share from each other.

Chapters:
0:00 GlobalFoundries in Photonics
1:21 GF's Photonics Strategy
3:02 GF's Market Leadership
5:06 300mm Wafer Advantage
6:55 Copper's Range Limits
9:18 Pluggable to CPO
13:48 CPO Reliability
19:22 OCI MSA Explained
26:20 GF's Scale Platform
29:04 Micro Mirror Technology
31:32 Photonics vs. Copper
38:25 Silicon Germanium Advantage

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How Retimers Built an $80B Company: The Story of Astera Labs Jul 31, 2026

Show notes

A retimer is a small, unglamorous chip. Astera turned it into a high-margin franchise. Austin and Vik cover why copper gives up at PCIe speeds, what a retimer does that a redriver can't, and how one H100 socket became a moat. Then Scorpio: can Astera take switch share from Broadcom?
Key Takeaways:
- 30cm of PCB trace at Gen 5's 32 GT/s and the signal is gone. Signal integrity is an inside-the-server problem, not just a rack-to-rack one.
- Gen 6 swaps NRZ for PAM4. Four voltage levels instead of two — a third the eye height, ~9.5 dB of SNR gone.
- A redriver amplifies, noise included. A retimer recovers the clock and data, rebuilds the signal, and resets the jitter budget.
- Astera won H100 by shipping PCIe 5 retimers at volume first, then bundling COSMOS on top. The chip became a fleet telemetry sensor.
- Sticky socket: H100 carried straight into an Aries 6 design-in on Blackwell.
- Scorpio moves up the stack. Same signal conditioning IP, higher ASP, pointed at Broadcom's PCIe switch business.
- Astera granted Amazon a warrant — 3.26M shares at $142.82, vesting against up to $6.5B of purchases through 2033. Equity flowing to the customer, and it sizes the Scorpio P-Series commitment behind Trainium 2 and 3.
Chapters:
0:00 The Astera Labs Franchise
3:32 The PCIe Copper Problem
6:53 Signal Smearing and Jitter
11:52 Eye Diagrams Explained
14:59 Equalization: Fixing the Signal
23:52 Redriver vs. Retimer
29:30 How Astera Won Nvidia
35:22 The Blackwell Scare
38:50 Scorpio: Moving into Switches
42:52 The UALink vs. Ethernet Battle
45:58 Taurus and Leo Product Lines
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News Take: Hyperscaler CDS, SK Hynix Earnings, China's DUV Jul 29, 2026

Show notes

Austin Lyons and Vik Sekar break down the market's recent volatility. They discuss the rising fear around hyperscaler debt, visible in credit default swap (CDS) premiums, and the counter-argument that GPU ROI is actually understated. They then analyze the paradox of SK Hynix's massive stock drop despite record growth, and explain why China's new DUV lithography tool makes 3D chip stacking essential to their strategy.

Key Takeaways:
* Hyperscaler debt fears are quantified by rising credit default swap (CDS) premiums, signaling investor nervousness that the AI CapEx firehose is shifting from cash flow to riskier debt.

* The counter-take on debt is that hyperscalers are under-earning on GPU assets — as long-term contracts re-price to spot rates 2x higher, the hardware's ROI will justify the financing.

* SK Hynix's 20% stock drop despite 257% YoY revenue growth shows a market priced for perfection, where a small miss against consensus triggers a panic disconnected from fundamentals.

* The memory market paradox: commodity DRAM is currently more profitable than HBM because HBM's production is 3x less bit-efficient per wafer, consuming scarce supply while DRAM spot prices soar.

* China's reported immersion DUV breakthrough is equivalent to ASML's late 2000s-era technology, a step toward self-sufficiency but not a leap to the leading edge.

Chapters:
0:00 The Market Is Freaking Out
0:21 Hyperscaler Debt and Credit Default Swaps
3:56 The Counter-Take: Under-Earning on GPUs
6:18 SK Hynix: Record Growth, Market Carnage
8:10 The HBM vs. DRAM Profitability Paradox
10:35 Leverage, Retail, and Panic Selling
12:05 China's Immersion DUV Breakthrough
13:28 The Limits of DUV: 7nm and Multi-Patterning
14:14 Logic Folding and 3D Stacking
16:12 A Long Journey to Self-Sufficiency
17:05 Surviving Semiconductor Cyclicality

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Datacenter Interconnects: Copper vs. Optics, Nvidia's 78-Layer PCB, Co-Packaged Optics (CPO) Jul 24, 2026

Show notes

Vik Sekar and Austin Lyons tackle the biggest bottleneck in inference: moving data. They break down the three tiers of datacenter networking — scale up, scale out, scale across — and the core engineering trade-off at each layer: copper vs. optics. Topics include Nvidia's extreme measures to keep scale-up fabric electrical (a 78-layer mid-plane PCB), why Co-Packaged Optics is the "holy grail" everyone wants and no one can ship, and the serviceability problem standing in its way.

Key Takeaways:

A single 72-GPU scale-up rack needs 5,000+ cables spanning ~2 km — at that density, the power and cost of every connection becomes a system-level constraint, not an implementation detail.
The scale-up rule is "copper when you can, optics when you must": each pluggable optical module adds ~30W, and with thousands of links in the fabric, that penalty compounds fast.
Nvidia is pushing copper past its usual limits with a 78-layer mid-plane PCB — 3x+ the layer count of a typical complex board — specifically to avoid paying the optics power tax in its scale-up fabric.
Scale-up isn't just a training problem. Frontier MoE models need 72-GPU domains to hit memory bandwidth targets, which pulls high-performance interconnect into the inference conversation.
Scale-up has the highest connection density of the three tiers, making it the largest TAM and the sharpest three-way fight between NVLink, UA-Link, and Ethernet.
Co-Packaged Optics could cut interconnect power by two-thirds — but a single failed laser could brick an entire multi-thousand-dollar GPU package, and that serviceability risk is what's keeping it on the roadmap instead of in racks.

Chapters:
0:00 The Biggest Problem in Computing
7:14 The Three Tiers of Networking
13:49 Scale Up: Copper vs. Optics
17:59 Front-End vs. Back-End Networks
22:12 The Physical Scale of Cabling
28:46 Nvidia's 78-Layer Mid-Plane
33:16 How Optical Transceivers Work
39:16 The Power Penalty of Pluggables
42:09 The Business of Speed Transitions
44:40 The Promise and Peril of CPO
51:45 The Holy Grail of Networking

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PicoJool's Al Yuen: The Case for GaAs VCSELs in Scale-Up Interconnects Jul 16, 2026

Show notes

Al Yuen, CEO of PicoJool, talks with Austin about using VCSELs for scale-up optical interconnects in AI data centers. Al explains why gallium arsenide (GaAs) supply is unconstrained while indium phosphide (InP) is limited, and how PicoJool can leverage existing supply chains to ship in the millions per month. They cover the roadmap from 1.6T to 12.8T, the trade-offs among 8×200G, 16×100G, and 32×50G, and the push to train the next generation of photonics engineers.

The spec that changed is error rate. AI needs error-free links (10⁻¹⁰–10⁻¹² vs Ethernet's old 10⁻⁶) because GPUs act as one system — one error stalls the whole job.
Single-mode optics can't hit the volume. Built for ~100K city-to-city links; datacenters need millions/month — a 10–50× gap
GaAs vs InP is the whole supply story. VCSELs run on unconstrained GaAs; single-mode on constrained InP. 1M units: 8–10 weeks vs a sold-out 8–18 months.
One platform, three flavors to 1.6T: 8×200G "fast and narrow," 16×100G LPO low-power, 32×50G NRZ "slow and wide" — pick on power, cost, and BER.
12.8T needs no new tech — just more of the same: 64 channels (4×16 array in a finger-sized connector) × 200G, scaling channels, bi-di wavelengths, and lane speed.
Capacity isn't the time consuming part — qualification is. WIN runs ~1,000 wafers/week at ~240K VCSELs each, so 1M units = ~10 wafers. The wait is tier-1 (>6 mo) and tier-2 (~3 mo) quals.

Chapters:
0:00 Meet Al Yuen and PicoJool
2:29 Inventing the active optical cable
5:03 Engineering mindset, copper limits
8:43 Why VCSELs
13:45 Scale-up and bit error rate
20:09 Unconstrained vs constrained supply
21:53 Indium phosphide bottleneck
25:49 VCSEL design and foundry handoff
31:59 Product road map, 200G launch
34:16 Path to 3.2T and 12.8T
40:10 Ordering a million VCSELs
45:10 Ramp timing and training new engineers
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WEKA's Val Bercovici: KV Cache, DeepSeek V4, HBF, SLC vs QLC NAND, CXL, NVLink, Tokenomics Jul 10, 2026

Show notes

Vik welcomes Val Bercovici from Weka to discuss the rapidly evolving landscape of AI memory and storage. Val explains how Weka's architecture leverages high-bandwidth networks to make storage faster than motherboard DRAM. They dive into KV cache optimizations, the future of NAND flash tiers, and the role of CXL in AI inference. The episode concludes with a look at predictive memory offloading and the AI flywheel.
Chapters:
0:00 Welcome Val Bercovici, Weka
1:59 Memory situation and model routing
3:50 KV cache offloading to CMX
6:10 Network faster than motherboard
13:10 Weka as AI memory infrastructure
14:45 Inference market is different
16:06 Memory hierarchy and KV cache
19:40 KV cache optimizations and demand
25:20 DeepSeek's cache read pricing
34:49 NAND flash tiers: SLC vs QLC
43:01 High Bandwidth Flash (HBF)
49:59 CXL versus other interconnects
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Micron's Record Profits, Apple's CXMT Plea: AI is Eating All the Memory Jul 03, 2026

Show notes

Austin and Vik break down the current memory crisis, where AI demand is driving unprecedented profits for memory makers like Micron, while simultaneously causing inflation and price hikes for consumer electronics. They discuss how even premium brands like Apple are struggling to secure supply, leading them to controversial suppliers. The hosts also explore the long-term implications of AI's insatiable memory appetite and its impact on both data center and consumer markets.
Chapters:
0:00 Memory crisis hits
1:20 AI impacting consumers
3:00 AI causing inflation
6:48 Consumer demand drop?
8:49 AI demand inelastic
10:56 Long-term memory outlook
11:02 GoPro's memory woes
12:24 Apple's pricing power
18:20 Apple seeks CXMT DRAM
21:38 Shrinkflation for phones
23:16 Korea's memory investment
26:10 Micron's killing profits
33:00 Why AI needs so much DRAM
40:27 Future of AI training
44:34 Cost-optimizing inference
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Qualcomm's HBC Memory, Alphawave, Modular, and more Jun 29, 2026

Show notes

Qualcomm flew Austin to New York for its investor day, where the communications company laid out a plan to make data center, automotive, and IoT two-thirds of its business by FY29. Austin was in the room and asked Cristiano Amon a question on the record. Vik watched the whole thing on YouTube. Together they break down what actually changed.

The technical centerpiece is High Bandwidth Compute (HBC): stacking LPDDR on top of logic to expose the whole face of the chip for interconnects, claiming up to 100x more lanes and a path around the HBM bandwidth bottleneck. Austin and Vik dig into what's really under that memory, why "no advanced packaging needed" just moves the hard problem somewhere worse, and how it compares to d-Matrix. And as Austin put it: don't let anyone tell you HBM is dead. MOAR memory.

Then the roadmap: the AI200/250/300 accelerators, the C1000 server CPU (5 GHz, 250+ cores, Meta as a customer), the Alphawave and Modular acquisitions, and Chris Lattner's Mojo.

The most interesting takeaway might not be the data center at all. Qualcomm's edge play — AI-defined vehicles, cars as token generators, and a $1T robotics opportunity by 2040 — could be where High Bandwidth Compute matters most.

Chapters:
0:00 Communications? That's just the start
4:08 Inside Qualcomm's investor day
9:16 Can Qualcomm build a data center business?
13:09 Disaggregated inference opens the door
17:57 High Bandwidth Compute: memory on the XPU
30:29 "No advanced packaging" just moves the problem
36:20 The roadmap, Alphawave, and Modular
46:00 The C1000 CPU and the agentic shortage
50:40 Cars as token generators, the $1T robotics bet
57:32 The memory market: MOAR

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Advanced Packaging, TSMC CoWoS, Intel EMIB Jun 19, 2026

Show notes

New episode: Advanced packaging for AI chips, from wire bonds to TSMC CoWOS and Intel EMIB.

Packaging is no longer an afterthought. It is the chip, and Intel's EMIB challenges TSMC's CoWOS.

Three CoWOS flavors: silicon, organic RDL, local bridges
EMIB embeds tiny bridges into the substrate, no interposer
EMIB-T and EMIB-M add through-silicon vias and power capacitors
Google is booking 3M TPUs on EMIB via MediaTek by 2028
Package sizes keep climbing: 5.5x reticle today, 40x ahead

This episode is brought to you by SambaNova. Try SambaNova's fast inference today at the SambaNova Dashboard!

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Chapters:
(0:00) "There Is No Chip Without the Packaging"
(0:28) Intro and SpaceX IPO Day
(5:15) What We're Covering: CoWOS, EMIB, Google
(7:40) Simple Packaging: Wire Bonds to Flip Chip
(17:07) What Makes Packaging "Advanced"
(33:44) CoWOS: Three Flavors Explained
(45:30) EMIB: Intel's Embedded Bridge Approach
(52:47) EMIB-T and EMIB-M
(57:31) CoWOS vs. EMIB Trade-offs
(1:02:18) Google's 3M TPU EMIB Order

Computex Mania 2026: Optics and Power Jun 12, 2026

Show notes

Austin and Vik discuss their recent experience at Computex, where they met for the first time in person after six months of podcasting together.
They share insights about the massive show, the people they connected with, and the exciting developments in AI hardware and interconnect technology.
Connect with Vik and Austin via a daily free newsletter:
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Vik's Paid Substack: https://www.viksnewsletter.com
Austin's Paid Substack: https://www.chipstrat.com
Chapters
00:00 Meeting in Person for the First Time
03:05 Experiencing Computex: A Massive Show
05:17 Connecting with the Audience: Real-Life Encounters
06:46 Networking with Industry Leaders
10:42 Keynote Highlights: Marvell's Vision
15:11 The Future of Interconnects: CPO and Beyond
22:54 Exploring Optical Interconnects and Future Technologies
25:56 Micro LED Developments and Future Conferences
27:34 Power Innovations in Data Centers
30:54 Intel's Keynote and New CPU Technologies
36:31 Intel Foundry's Advancements and Industry Implications

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